[–] akoboldfrying 20 hours ago
The hairsplitting nerd in me can't help but point out that the claim in the Part 2 article that the problem of combining deltas is NP hard isn't true. In fact you can solve this optimally in O(n^3) time with DP: Let g(i, j) be the minimum number of bytes needed to encode input deltas i..j as a single (i.e., combined) output delta. Given g(i, j), computing g(i, j+1) takes constant time, so we can compute all of this function's values in O(n^2) total time. Now let f(i, j) be the minimum number of bytes needed to encode input deltas i..j using any sequence of output deltas (combined or not). Note that any such sequence must consist of some number (possibly zero) of optimally encoded output deltas followed by an optimally encoded output delta that itself ends with input delta j. IOW, it must be that f(i, j) is equal to f(i, k) + g(k+1, j) for some k, and there are at most n values of k that we need to try, so we can compute each value of f() in O(n); there are O(n^2) values to compute, so O(n^3) time overall. f(1, n) is then the minimum number of bytes needed to encode the entire list of input deltas, and standard backtracing through the DP matrix can be used to recover the actual sequence of output deltas.
[–] Agingcoder 20 hours ago
[–] blackhaz 14 hours ago
[–] benlivengood 11 hours ago
Direct access to the text mode segment (0xb800 if I remember correctly) was much faster. The fonts were blitted out by hardware for every scan line, so you just changed the few thousand bytes of video memory at hundreds of thousands of bytes per second.
[–] kragen 3 hours ago
[–] Tuna-Fish 2 hours ago
The actual usable bandwidth was always much lower, somewhere between 80kB/s to a bit over 380kB/s, depending on how you were using the bus, because the cpu needed to fetch its instructions on the same bus. In a way, the bus was usually always running at 1.19MB/s though, because all the basic devices (ROM, RAM, common simple ISA cards) were able to always respond in the basic 4-cycle transfer, it's just that most cycles were spent fetching instructions instead of actual data.
Later machines made the bus faster by increasing width, increasing clocks, and dropping one mandatory wait state at AT for 5.55MB/s theoretical, and dropping the last wait state in the fast clones for 8.33MB/s theoretical.
[–] akoboldfrying 2 minutes ago
[–] kragen 1 hour ago
[–] badc0ffee 1 hour ago
[–] kragen 1 hour ago
[–] vasac 13 hours ago