The 8-bit ISA bus was theoretically capable of 1.19MB/s. The bus architecture always took 4 cycles per transfer (enforced by the 8288 which had a 4-cycle state machine, iirc one cycle for address, one for data, and two wait states), transferred 8 bits per transfer, and ran at the 4.77MHz frequency.

The actual usable bandwidth was always much lower, somewhere between 80kB/s to a bit over 380kB/s, depending on how you were using the bus, because the cpu needed to fetch its instructions on the same bus. In a way, the bus was usually always running at 1.19MB/s though, because all the basic devices (ROM, RAM, common simple ISA cards) were able to always respond in the basic 4-cycle transfer, it's just that most cycles were spent fetching instructions instead of actual data.

Later machines made the bus faster by increasing width, increasing clocks, and dropping one mandatory wait state at AT for 5.55MB/s theoretical, and dropping the last wait state in the fast clones for 8.33MB/s theoretical.