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points by duskwuff 2 days ago | 0 comments
> Even less "quirky" but fully open source designs like GateMate have very poor fmax and utilization in my experience.

The terrible Fmax on GateMate is specifically a result of its "quirky" design. There's no dedicated clock network on the part - clocks have to be routed through fabric just like everything else. Running those signals everywhere consumes routing capacity and incurs delays; the resulting clock skew is awful.

[–] imtringued 2 days ago
That type of design seems highly resistant to classic fmax raising techniques like pipelining because pipelining can't fix clock skew.
[–] Paul_Clayton 20 hours ago
A pipeline can tolerate clock offsets. E.g., an ALU like the Pentium 4's staggered ALU but within "a single clock cycle" might allow the more significant input bits to arrive at a time offset relative to the time for the first bits of inputs. Parsing variable length encoded instructions has a similar "carry propagation". Similarly, different stages might use different amounts of the cycle. Grid network routing can also localize time synchronization.

Getting the clock routing delay to approximate the delay that is designed to be tolerated seems likely to be rather tricky, but I think clock offsets from imbalanced travel distance do not have to make all of that time wasted.

I might well be wrong as I am only aware of some very general concepts of hardware design. Even in my ignorance, I am aware that theoretically possible in some cases is not the same as practical/worthwhile in general.