I've been out of the FPGA scene for a while, is the big idea of hard NoC that you can use network/packet abstractions to send data between larger subcomponents as opposed to routing through FPGA fabric and sweating the buffers/timing yourself?
Yeah, basically instead of consuming registers (or HyperRegisters when it's able to move them into the routing fabric during HyperRetiming) the NoC can be used to connect the main hard IPs to logic on the fabric without necessarily having to locate that logic directly near the pins.
On recent Agilex 7 the NoC exists but is fairly primitive and can only be used for DDR (and maybe HBM?) and it adds latency over direct pin access and has some other downsides that escape my memory right now.
The AMD FPGAs on the other hand have a very powerful and flexible NoC that runs both vertically and horizontally across the die and can be used to not just connect to hard IPs but also user logic across the die.
My hope is this new NoC is much more like AMD implementation, even if it can only do stuff like: Hard IP => Fabric => Hard IP as long as you can use it to connect F-Tile/R-Tile and not just DRAM that will be huge already in terms of saving massive amounts of fabric that otherwise gets eaten up by huge busses.
[–] smallmancontrov 2 days ago
[–] jpgvm 2 days ago
On recent Agilex 7 the NoC exists but is fairly primitive and can only be used for DDR (and maybe HBM?) and it adds latency over direct pin access and has some other downsides that escape my memory right now.
The AMD FPGAs on the other hand have a very powerful and flexible NoC that runs both vertically and horizontally across the die and can be used to not just connect to hard IPs but also user logic across the die.
My hope is this new NoC is much more like AMD implementation, even if it can only do stuff like: Hard IP => Fabric => Hard IP as long as you can use it to connect F-Tile/R-Tile and not just DRAM that will be huge already in terms of saving massive amounts of fabric that otherwise gets eaten up by huge busses.